As the size of MOS transistor features continues to shrink, some dopants used to fabricate the transistors are implanted at shallower depths. Specifically, so-called “ultra-shallow” junctions are thought to successfully improve device performance with scaling. These junctions generally provide better threshold voltage control, improve transistor performance, reduce CHC (Channel Hot Carrier) degradation and reduce parasitic capacitance.
In the past, an implant process could be characterized by physical contact with a metrology wafer into which the dopant is implanted using the production process. When the implant energy of a dopant is sufficiently high, and the implant depth sufficiently large, four-point measurement may be used to determine the resistivity of the metrology wafer. However, when the depth of the doped region is less than about the spacing between electrodes used for four-point measurement, electric field lines of the four-point probe may extend below the doped layer.
In this case the measured resistivity may be dominated by the undoped substrate below the doped layer. Thus, four-point measurement of test doped layers formed by shallow implants may not accurately represent the characteristics of the doped layer. As a result, sheet resistance measurements become unreliable for manufacturing purposes. This limitation is particularly applicable for shallow implants used in MOS transistor technology associated with a transistor gate length of about 45 nm or less.
Accordingly, what is needed in the art is a method of characterizing shallow junction implant processes that overcomes the limitations of the prior art.